Please use this identifier to cite or link to this item: http://hdl.handle.net/1942/25376
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dc.contributor.authorLI, Yanzhe-
dc.contributor.authorHuang, Kai-
dc.contributor.authorCLAESEN, Luc-
dc.date.accessioned2018-01-03T09:34:27Z-
dc.date.available2018-01-03T09:34:27Z-
dc.date.issued2017-
dc.identifier.citationSantambrogio, Marco; Gohringer, Diana; Stroobandt, Dirk; Mentens, Nele; Nurmi, Jari (Ed.). Proceedings of the 27th International Conference on Field-Programmable Logic and Applications, FPL-2017, IEEE Institute of Electrical and Electronics Engineers,p. 5B-1-5B-6-
dc.identifier.isbn9789090304281-
dc.identifier.issn1946-1488-
dc.identifier.urihttp://hdl.handle.net/1942/25376-
dc.description.abstractThree dimensional (3D) vision applications have drawn more attention nowadays and many products are entering the mass market. View interpolation is a crucial step to generate intermediate viewpoints from reference images. However, it is still challenging to achieve good performance in both processing speed and image quality for various 3D applications. In this paper, a hardware-compatible view interpolation algorithm is proposed, which can produce high-quality intermediate images by disparity warping and color blending. Moreover, a fully pipelined hardware architecture is designed based on the algorithm. A prototype of the proposed architecture has been implemented on an Altera Stratix-IV FPGA board, achieving 65 frames per second (fps) with a full HD (1920 1080) resolution. It is evaluated on the Middlebury benchmark quantitatively, and visual results of realworld images are also provided.-
dc.description.sponsorshipFWO-
dc.language.isoen-
dc.publisherIEEE Institute of Electrical and Electronics Engineers-
dc.relation.ispartofseriesInternational Conference on Field Programmable and Logic Applications-
dc.rightsIEEE Xplore-
dc.subject.othersystem-on-chip design; FPGA; 3D vision; view interpolation; depth images; disparity-
dc.titleHigh-Quality View Interpolation Based on Depth Maps and Its Hardware Implementation-
dc.typeProceedings Paper-
local.bibliographicCitation.conferencedate04-08/09/2017-
local.bibliographicCitation.conferencenameFLP 2017 - 27th International Conference on Field-Programmable Logic and Applications-
local.bibliographicCitation.conferenceplaceGhent, Belgium-
dc.identifier.epage5B-6-
dc.identifier.spage5B-1-
local.bibliographicCitation.jcatC1-
dc.description.notesLi, YZ (reprint author), Zhejiang Univ, Inst VLSI Design, Hangzhou, Zhejiang, Peoples R China. liyz@vlsi.zju.edu.cn; huangk@vlsi.zju.edu.cn; luc.claesen@uhasselt.be-
local.publisher.placeNew York (NY), USA-
dc.relation.references[1] N. A. Dodgson, “Autostereoscopic 3D displays,” Computer, vol. 38, no. 8, pp. 31–36, Aug 2005. [2] R. Szeliski, Computer Vision: Algorithms and Applications. Springer, 2010. [3] S. E. Chen and L. Williams, “View interpolation for image synthesis,” in Proceedings of the 20th Annual Conference on Computer Graphics and Interactive Techniques, ser. SIGGRAPH ’93. New York, NY, USA: ACM, 1993, pp. 279–288. [4] L. Zhang, D. Wang, and A. Vincent, “Adaptive reconstruction of intermediate views from stereoscopic images,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 16, no. 1, pp. 102–113, Jan 2006. [5] K. Wegner, O. Stankiewicz, M. Tanimoto, and M. Domanski, “Enhanced view synthesis reference software (VSRS) for freeviewpoint television,” Technical Report ISO/IEC JTC1/SC29/WG11 M31520, MPEG, October 2013. [6] E. Bondarev, S. Zinger, and P. H. N. de With, “Performance-efficient architecture for free-viewpoint 3DTV receiver,” in 2010 Digest of Technical Papers International Conference on Consumer Electronics (ICCE), Jan 2010, pp. 65–66. [7] L. Do, G. Bravo, S. Zinger, and P. H. N. de With, “Real-time freeviewpoint DIBR on GPUs for large base-line multi-view 3DTV videos,” in 2011 Visual Communications and Image Processing (VCIP), Nov 2011, pp. 1–4. [8] A. Akin, R. Capoccia, J. Narinx, J. Masur, A. Schmid, and Y. Leblebici, “Real-time free viewpoint synthesis using three-camera disparity estimation hardware,” in 2015 IEEE International Symposium on Circuits and Systems (ISCAS), May 2015, pp. 2525–2528. [9] http://vision.middlebury.edu/stereo/. [10] K. Takahashi, “View interpolation sensitive to pixel positions,” in 2013 IEEE International Conference on Image Processing, Sept 2013, pp. 2207–2211. [11] Y. Li, K. Huang, and L. Claesen, “Soc oriented real-time high-quality stereo vision system,” in 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Sept 2016, pp. 1–6. [12] Z. Wang, A. C. Bovik, H. R. Sheikh, and E. P. Simoncelli, “Image quality assessment: from error visibility to structural similarity,” IEEE Transactions on Image Processing, vol. 13, no. 4, pp. 600–612, April 2004. [13] G. Fhr, G. P. Fickel, L. P. Dal’Aqua, C. R. Jung, T. Malzbender, and R. Samadani, “An evaluation of stereo matching methods for view interpolation,” in 2013 IEEE International Conference on Image Processing, Sept 2013, pp. 403–407.-
local.type.refereedRefereed-
local.type.specifiedProceedings Paper-
dc.identifier.doi10.23919/FPL.2017.8056787-
dc.identifier.isi000426989400032-
local.bibliographicCitation.btitleProceedings of the 27th International Conference on Field-Programmable Logic and Applications, FPL-2017-
item.fullcitationLI, Yanzhe; Huang, Kai & CLAESEN, Luc (2017) High-Quality View Interpolation Based on Depth Maps and Its Hardware Implementation. In: Santambrogio, Marco; Gohringer, Diana; Stroobandt, Dirk; Mentens, Nele; Nurmi, Jari (Ed.). Proceedings of the 27th International Conference on Field-Programmable Logic and Applications, FPL-2017, IEEE Institute of Electrical and Electronics Engineers,p. 5B-1-5B-6.-
item.contributorLI, Yanzhe-
item.contributorHuang, Kai-
item.contributorCLAESEN, Luc-
item.validationecoom 2019-
item.accessRightsRestricted Access-
item.fulltextWith Fulltext-
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