Please use this identifier to cite or link to this item: http://hdl.handle.net/1942/25924
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dc.contributor.authorLI, Yanzhe-
dc.contributor.authorHuang, Kai-
dc.contributor.authorCLAESEN, Luc-
dc.date.accessioned2018-04-18T14:55:52Z-
dc.date.available2018-04-18T14:55:52Z-
dc.date.issued2017-
dc.identifier.citationHollstein, Thomas; Raik, Jaan; Kostin, Sergei; Tšertov, Anton; O'Connor, Ian; Reis, Ricardo (Ed.). VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability, Springer Nature, p. 213-232-
dc.identifier.isbn9783319671031-
dc.identifier.issn1868-4238-
dc.identifier.urihttp://hdl.handle.net/1942/25924-
dc.description.abstractStereo matching is a crucial step to extract depth information from stereo images. However, it is still challenging to achieve good performance in both speed and accuracy for various stereo vision applications. In this contribution, a hardware-compatible stereo matching algorithm is proposed and its associated hardware implementation is also presented. The proposed algorithm can produce high-quality disparity maps with the combined use of the mini-census transform, segmentation-based adaptive support weight and effective refinement. Moreover, the proposed architecture is optimized as a fully pipelined and scalable hardware system. Implemented on an Altera Stratix-IV FPGA board, it can achieve 65 frames per second (fps) for 1024 × 768 stereo images and a 64 pixel disparity range. The proposed system is evaluated on the Middlebury benchmark and the average error rate is 6.56%. The experimental results indicate that the accuracy is competitive with some state-of-the-art software implementations.-
dc.description.sponsorshipThe research in this contribution was sponsored in part by the Belgian FWO (Flemish Research Council) and the Chinese MOST (Ministry of Science and Technology) bilateral cooperation project number G.0524.13.-
dc.language.isoen-
dc.publisherSpringer-Verlag-
dc.relation.ispartofseriesIFIP Advances in Information and Communication Technology-
dc.rights(c) IFIP International Federation for information Processing 2017-
dc.subject.otherstereo matching; hardware implementation; system-on-chip; fpga; disparity calculation; computer vision.-
dc.titleA Novel Hardware-Oriented Stereo Matching Algorithm and Its Architecture Design in FPGA-
dc.typeProceedings Paper-
local.bibliographicCitation.authorsHollstein, Thomas-
local.bibliographicCitation.authorsRaik, Jaan-
local.bibliographicCitation.authorsKostin, Sergei-
local.bibliographicCitation.authorsTšertov, Anton-
local.bibliographicCitation.authorsO'Connor, Ian-
local.bibliographicCitation.authorsReis, Ricardo-
local.bibliographicCitation.conferencedate26-28/09/2016-
local.bibliographicCitation.conferencename24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration ( VLSI-SoC)-
local.bibliographicCitation.conferenceplaceTallinn, Estonia-
dc.identifier.epage232-
dc.identifier.spage213-
local.bibliographicCitation.jcatC1-
dc.description.notesLi, YZ (reprint author), Zhejiang Univ, Inst VLSI Design, Hangzhou, Zhejiang, Peoples R China. liyz@vlsi.zju.edu.cn; huangk@vlsi.zju.edu.cn; luc.claesen@uhasselt.be-
local.publisher.placeBerlin, Germany-
dc.relation.references1. Scharstein, D., Szeliski, R.: A taxonomy and evaluation of dense two-frame stereo correspondence algorithms. Int. J. Comput. Vis. 47, 7–42 (2002) CrossRefMATHGoogle Scholar 2. Hirschmuller, H., Scharstein, D.: Evaluation of cost functions for stereo matching. In: IEEE Conference on Computer Vision and Pattern Recognition, pp. 1–8. IEEE Press, Minneapolis (2007) Google Scholar 3. Veksler, O.: Stereo correspondence by dynamic programming on a tree. In: IEEE Conference on Computer Vision and Pattern Recognition, pp. 384–390. IEEE Press, San Diego (2005) Google Scholar 4. Klaus, A., Sormann, M., Karner, K.: Segment-based stereo matching using belief propagation and a self-adapting dissimilarity measure. In: 18th International Conference on Pattern Recognition (ICPR 2006), pp. 15–18. IEEE Press, Hang Kong (2006) Google Scholar 5. Kang, S.B., Szeliski, R., Chai, J.: Handling occlusions in dense multi-view stereo. In: IEEE Conference on Computer Vision and Pattern Recognition, pp. 103–110. IEEE Press, Kauai (2001) Google Scholar 6. Hirschmuller, H.: Accurate and efficient stereo processing by semiglobal matching and mutual information. In: IEEE Conference on Computer Vision and Pattern Recognition, pp. 807–814, San Diego (2005) Google Scholar 7. Kanade, T., Okutomi, M.: A stereo matching algorithm with an adaptive window: theory and experiment. IEEE Trans. Pattern Anal. Mach. Intell. 16, 920–932 (1994) CrossRefGoogle Scholar 8. Yoon, K.-J., Kweon, I.-S.: Adaptive support-weight approach for correspondence search. IEEE Trans. Pattern Anal. Mach. Intell. 28, 650–656 (2006) CrossRefGoogle Scholar 9. Tombari, F., Mattoccia, S., Stefano, L.: Segmentation-based adaptive support for accurate stereo correspondence. In: Mery, D., Rueda, L. (eds.) PSIVT 2007. LNCS, vol. 4872, pp. 427–438. Springer, Heidelberg (2007). doi: 10.1007/978-3-540-77129-6_38 CrossRefGoogle Scholar 10. Ttofis, C., Theocharides, T.: Towards accurate hardware stereo correspondence: a real-time FPGA implementation of a segmentation-based adaptive support weight algorithm. In: Proceedings of the Conference on Design, Automation & Test in Europe, Conference and Exhibition (DATE), pp. 703–708. IEEE Press, Germany (2012) Google Scholar 11. Middlebury benchmark. http://vision.middlebury.edu/stereo/ 12. Chang, N.Y.-C., Tsai, T.-H., Hsu, B.-H., Chen, Y.-C., Chang, T.-S.: Algorithm and architecture of disparity estimation with mini-census adaptive support weight. IEEE Trans. Circ. Syst. Video Technol. 20, 792–805 (2010) CrossRefGoogle Scholar 13. Zhang, L., Zhang, K., Chang, T.S., Lafruit, G., Kuzmanov, G.K., Verkest, D.: Real-time high-definition stereo matching on FPGA. In: 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pp. 55–64. ACM Press, Monterey (2011) Google Scholar 14. Akin, A., Baz, I., Schmid, A., Leblebici, Y.: Dynamically adaptive real-time disparity estimation hardware using iterative refinement. Integr. VLSI J. 47, 365–376 (2014) CrossRefGoogle Scholar 15. Shan, Y., Wang, Z., Hao, Y., Wang, Y., Tsoi, K., Luk, W., Yang, H.: FPGA based memory efficient high resolution stereo vision system for video tolling. In: International Conference on Field-Programmable Technology (FPT), pp. 29–32. IEEE Press, Seoul (2012) Google Scholar 16. Zhang, K., Lu, J., Lafruit, G., Lauwereins, R., Gool, L.V.: Real-time accurate stereo with bitwise fast voting on CUDA. In: 12th International Conference on Computer Vision Workshops (ICCV Workshops), pp. 794–800. IEEE Press, Kyoto (2009) Google Scholar 17. Shan, Y., Hao, Y., Wang, W., Wang, Y., Chen, X., Yang, H., Luk, W.: Hardware acceleration for an accurate stereo vision system using mini-census adaptive support region. ACM Trans. Embed. Comput. Syst. 13, 1–24 (2014) CrossRefGoogle Scholar 18. Wang, W., Yan, J., Xu, N., Wang, Y., Hsu, F.H.: Real-time high-quality stereo vision system in FPGA. In: International Conference on Field-Programmable Technology (FPT), pp. 358–361. IEEE Press, Kyoto (2013) Google Scholar 19. Mei, X., Sun, X., Zhou, M., Jiao, S., Wang, H., Zhang, X.: On building an accurate stereo matching system on graphics hardware. In: 14th International Conference on Computer Vision Workshops (ICCV Workshops), pp. 467–474. IEEE Press, Barcelona (2011) Google Scholar 20. Yang, Q., Li, D., Wang, L., Zhang, M.: Fast local stereo matching using two-level adaptive cost filtering. In: International Conference on Acoustics, Speech and Signal Processing, pp. 1986–1990. IEEE Press, Vancouver (2013) Google Scholar 21. Zhang, K., Lu, J., Lafruit, G.: Cross-based local stereo matching using orthogonal integral images. IEEE Trans. Circ. Syst. Video Technol. 19, 1073–1079 (2009) CrossRefGoogle Scholar 22. Hirschmuller, H.: Stereo processing by semiglobal matching and mutual information. IEEE Trans. Pattern Anal. Mach. Intell. 30, 328–341 (2008) CrossRefGoogle Scholar-
local.type.refereedRefereed-
local.type.specifiedProceedings Paper-
local.relation.ispartofseriesnr508-
dc.identifier.doi10.1007/978-3-319-67104-8_11-
dc.identifier.isi000432573400011-
local.bibliographicCitation.btitleVLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability-
item.validationecoom 2019-
item.fulltextWith Fulltext-
item.accessRightsRestricted Access-
item.fullcitationLI, Yanzhe; Huang, Kai & CLAESEN, Luc (2017) A Novel Hardware-Oriented Stereo Matching Algorithm and Its Architecture Design in FPGA. In: Hollstein, Thomas; Raik, Jaan; Kostin, Sergei; Tšertov, Anton; O'Connor, Ian; Reis, Ricardo (Ed.). VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability, Springer Nature, p. 213-232.-
item.contributorLI, Yanzhe-
item.contributorHuang, Kai-
item.contributorCLAESEN, Luc-
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