Please use this identifier to cite or link to this item: http://hdl.handle.net/1942/26697
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dc.contributor.authorMOTTEN, Andy-
dc.contributor.authorCLAESEN, Luc-
dc.contributor.authorPan, Yun-
dc.date.accessioned2018-08-24T13:28:05Z-
dc.date.available2018-08-24T13:28:05Z-
dc.date.issued2013-
dc.identifier.citationBurg, Andreas; Coṣkun, Ayse; Guthaus, Matthew; Katkoori, Srinivas; Reis, Ricardo (Ed.). Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip VLSI-SoC 2012: VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, Springer,p. 45-63-
dc.identifier.isbn9783642450723-
dc.identifier.issn1868-4238-
dc.identifier.urihttp://hdl.handle.net/1942/26697-
dc.description.abstractA real-time trinocular stereo vision processor is proposed which combines a window matching architecture with a classification architecture. A pair wise segmented window matching for both the center-right and center-left image pairs as their scaled down image pairs is performed. The resulting cost functions are combined which results into nine different cost curves. A multi level hierarchical classifier is used to select the most promising disparity value. The classifier makes use of features provided by the calculated cost curves and the pixels’ spatial neighborhood information. Evaluation and classifier training has been performed using an indoor dataset. The system is prototyped on an FPGA board equipped with three CMOS cameras. Special care has been taken to reduce the latency and the memory footprint.-
dc.description.sponsorshipThis research has been sponsored in part by the BOF (Bijzonder Onderzoeks Fonds uHasselt), Flanders FWO (Fonds voor Wetenschappelijk Onderzoek) and Chinese MOST (Ministry of Science and Technology) project number G.A.063.10.-
dc.language.isoen-
dc.publisherSpringer-
dc.relation.ispartofseriesIFIP Advances in Information and Communication Technology-
dc.rights© IFIP International Federation for Information Processing 2013-
dc.subject.othertrinocular stereo camera; real-time matching; confidence metric; computer vision; system-on-chip; FPGA; SoC-
dc.titleTrinocular Stereo Vision Using a Multi Level Hierarchical Classification Structure-
dc.typeProceedings Paper-
local.bibliographicCitation.authorsBurg, Andreas-
local.bibliographicCitation.authorsCoṣkun, Ayse-
local.bibliographicCitation.authorsGuthaus, Matthew-
local.bibliographicCitation.authorsKatkoori, Srinivas-
local.bibliographicCitation.authorsReis, Ricardo-
local.bibliographicCitation.conferencedate07-10/10/2012-
local.bibliographicCitation.conferencename20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2012)-
local.bibliographicCitation.conferenceplaceDream Inn, Santa Cruz, USA-
dc.identifier.epage63-
dc.identifier.spage45-
local.bibliographicCitation.jcatC1-
local.publisher.placeBerlin, Germany-
local.type.refereedRefereed-
local.type.specifiedProceedings Paper-
local.relation.ispartofseriesnr418-
dc.identifier.doi10.1007/978-3-642-45073-0_3-
local.bibliographicCitation.btitleProceedings of the IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip VLSI-SoC 2012: VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design-
item.contributorMOTTEN, Andy-
item.contributorCLAESEN, Luc-
item.contributorPan, Yun-
item.fullcitationMOTTEN, Andy; CLAESEN, Luc & Pan, Yun (2013) Trinocular Stereo Vision Using a Multi Level Hierarchical Classification Structure. In: Burg, Andreas; Coṣkun, Ayse; Guthaus, Matthew; Katkoori, Srinivas; Reis, Ricardo (Ed.). Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip VLSI-SoC 2012: VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, Springer,p. 45-63.-
item.accessRightsRestricted Access-
item.fulltextWith Fulltext-
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