Two-topology based high-level simulation platform for NoC performance evaluation

Abstract

Aiming at realizing efficient performance evaluation of NoC, and reducing SoC (system-on-chip) development period, this paper proposes a new high-level, high-efficiency, cycle accurate NoC simulation platform. Different from conventional tools, it supports evaluation for both 2D mesh and ring topologies and virtual channel extension in router structure design. It efficiently gives performance results, including average latency, throughput and energy consumption. Experimental results demonstrate that this simulation platform can simulate NoC behavior and obtain performance evaluation results, which provides high-efficiency verification method for NoC design and optimization.