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http://hdl.handle.net/1942/31566
Title: | Interface and Border Traps in Ge-Based Gate Stacks | Authors: | Nyns, L. LIN, Dan BRAMMERTZ, Guy Bellenger, F. Shi, X. Sioncke, S. Van Elshocht, S. Caymax, M. |
Issue Date: | 2011 | Publisher: | ELECTROCHEMICAL SOC INC | Source: | DIELECTRICS IN NANOSYSTEMS -AND- GRAPHENE, GE/III-V, NANOWIRES AND EMERGING MATERIALS FOR POST-CMOS APPLICATIONS 3, ELECTROCHEMICAL SOC INC, p. 465 -480 | Abstract: | A critical issue for the successful integration of Ge devices into future high-performance technology nodes is the electrical passivation of the Ge surface. We have examined this electrical passivation in terms of interface and border traps for several Ge-based gate stacks, where we varied amongst others the GeO2 thickness, the high-k material and the Post Deposition Anneal (PDA). The GeO2 thickness seems to have the largest impact, and an inverse relation between the density of interface traps D-it and border traps N-bt exists for GeO2 layers up to similar to 2 nm. We found that the most optimal passivation is achieved by using an (almost) oxide-free surface as this would result in the lowest Nbt. Although such a surface is characterized by a high mid-gap Dit, this can be improved by performing the correct PDA. We conclude that the most promising oxide-free surface is obtained after an H2S treatment. | Notes: | Nyns, L (corresponding author), IMEC, Kapeldreef 75, B-3001 Louvain, Belgium. | Document URI: | http://hdl.handle.net/1942/31566 | ISBN: | 978-1-60768-214-1 978-1-56677-864-0 |
ISSN: | 2515-7655 | e-ISSN: | 2515-7655 | DOI: | 10.1149/1.3569938 | ISI #: | WOS:000309539300043 | Category: | C1 | Type: | Proceedings Paper |
Appears in Collections: | Research publications |
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