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Title: | Selective Epitaxial Growth of InP in STI Trenches on Off-Axis Si (001) Substrates | Authors: | Wang, G. Nguyen, N. D. Leys, M. R. Loo, R. BRAMMERTZ, Guy Richard, O. Bender, H. Dekoster, J. MEURIS, Marc Heyns, M. M. Caymax, M. |
Issue Date: | 2010 | Publisher: | ELECTROCHEMICAL SOC INC | Source: | CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2010 (CSTIC 2010), ELECTROCHEMICAL SOC INC, p. 959 -964 | Series/Report: | ECS Transactions | Series/Report no.: | 27 | Abstract: | We report high quality InP layers selectively grown in shallow trench isolation structures on 6 degrees offcut Si (001) substrates capped with a thin Ge buffer layer. The Ge layer was used to reduce the thermal budget for surface clean and double step formation. The atomic steps on the Ge surface were recovered after a bake at 680 degrees C. Smooth nucleation layer was obtained at 420 degrees C on the Ge surface. Baking the Ge surface in As ambient facilitates the InP nucleation and improves the InP crystalline quality. This improvement is attributed to the effective As adsorption on the Ge surface and the polar Ge: As surface prevents the islanding of InP seed layer. Stacking faults were found in the InP layers as a result of threading dislocation dissociation and high quality InP layers were obtained in trenches with aspect ratios greater than 2. | Notes: | Wang, G (corresponding author), IMEC, Kapeldreef 75, B-3001 Louvain, Belgium. | Keywords: | GE | Document URI: | http://hdl.handle.net/1942/31589 | ISBN: | 978-1-60768-156-4 | DOI: | 10.1149/1.3360736 | ISI #: | WOS:000313327800149 | Category: | C1 | Type: | Proceedings Paper |
Appears in Collections: | Research publications |
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