Interfaces of high-k dielectrics on GaAs: Their common features and the relationship with Fermi level pinning (Invited Paper)

Abstract

Numerous metal oxides have been studied worldwide as possible high-k gate dielectric candidates for MOS devices on alternative semiconductor materials (Ge, III/V compounds). We will discuss thermal and plasma-enhanced atomic layer deposition (ALD) of a few materials, HfO(2) and Al(2)O(3), We will spend some attention to characteristic features of the growth process and specific growth precursors as this is known to influence strongly the quality of the layer bulk as well as the interface. Detailed electrical characterization of MOS capacitors build on such dielectric layers, before and after forming gas anneals, shows that these interface modifications can lead to a marked decrease of the smaller interface state peaks close to the edges of the bandgap, whereas the larger mid-gap peaks are barely touched. The results of atomistic modeling of the oxidation of a GaAs surface help to understand the origin of these mid-gap electronic states, which are responsible for the apparent pinning of the Fermi level. (C) 2009 Elsevier B.V. All rights reserved.