Please use this identifier to cite or link to this item: http://hdl.handle.net/1942/7782
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dc.contributor.authorLeaming-Sphabmixay, K.-
dc.contributor.authorVAN OLMEN, Jan-
dc.contributor.authorMoon, K. J.-
dc.contributor.authorVANSTREELS, Kris-
dc.contributor.authorD'HAEN, Jan-
dc.contributor.authorTokei, Z.-
dc.contributor.authorList, S.-
dc.contributor.authorBeyer, G.-
dc.date.accessioned2008-02-01T16:32:19Z-
dc.date.available2008-02-01T16:32:19Z-
dc.date.issued2007-
dc.identifier.citationMICROELECTRONIC ENGINEERING, 84(11). p. 2681-2685-
dc.identifier.issn0167-9317-
dc.identifier.urihttp://hdl.handle.net/1942/7782-
dc.description.abstractThe fabrication of narrow Cu trenches using a conformal TEOS backfill approach is shown. Cu trenches with widths down to 3040 nm were achieved. With an adequate Ta-based PVD barrier and Cu seed layer scheme, narrow Cu lines with high yield were obtained. An increase of the electrical resistivity in the narrowest dimensions was observed as a result of the size effect. Electromigration assessment demonstrated that a bilayer TaN/Ta barrier outperforms the monolayer Ta barrier. Electron backscattering diffraction (EBSD) analysis was carried out to determine grain orientation and texture in narrow copper trenches. For the first time, EBSD data reveal that Cu trenches down to 30-40 run wide have mostly a random texture. The narrower the Cu lines get, the weaker the (I 11) texture with both monolayer and bilayer Ta-based barriers. (c) 2001 Published by Elsevier B.V.-
dc.language.isoen-
dc.publisherELSEVIER SCIENCE BV-
dc.subject.othermetallization and barrier materials, interconnects, process integration, effect of scaling-
dc.titleElectrical performance, reliability and microstructure of sub-45 nm copper damascene lines fabricated with TEOS backfill-
dc.typeJournal Contribution-
local.bibliographicCitation.conferencedateBruges, BELGIUM-
local.bibliographicCitation.conferencename16th European Workshop on Materials for Advanced Metallization-
dc.identifier.epage2685-
dc.identifier.issue11-
dc.identifier.spage2681-
dc.identifier.volume84-
local.format.pages5-
local.bibliographicCitation.jcatA1-
dc.description.notesIMEC, Louvain, B-3001 Belgium. Hasselt Univ, Inst Mat Res, Diepenbeek, B-3590 Belgium. Div IMOMEC, Diepenbeek, B-3590 Belgium.Van Olmen, J, IMEC, Kapeldreef 75, Louvain, B-3001 Belgium.-
local.type.refereedRefereed-
local.type.specifiedArticle-
dc.bibliographicCitation.oldjcatA1-
dc.identifier.doi10.1016/j.mee.2007.06.009-
dc.identifier.isi000250657200045-
item.accessRightsClosed Access-
item.contributorLeaming-Sphabmixay, K.-
item.contributorVAN OLMEN, Jan-
item.contributorMoon, K. J.-
item.contributorVANSTREELS, Kris-
item.contributorD'HAEN, Jan-
item.contributorTokei, Z.-
item.contributorList, S.-
item.contributorBeyer, G.-
item.fulltextNo Fulltext-
item.fullcitationLeaming-Sphabmixay, K.; VAN OLMEN, Jan; Moon, K. J.; VANSTREELS, Kris; D'HAEN, Jan; Tokei, Z.; List, S. & Beyer, G. (2007) Electrical performance, reliability and microstructure of sub-45 nm copper damascene lines fabricated with TEOS backfill. In: MICROELECTRONIC ENGINEERING, 84(11). p. 2681-2685.-
item.validationecoom 2008-
crisitem.journal.issn0167-9317-
crisitem.journal.eissn1873-5568-
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