Please use this identifier to cite or link to this item:
http://hdl.handle.net/1942/11273
Title: | A Binary Adaptable Window SoC Architecture for a StereoVision Based Depth Field Processor | Authors: | MOTTEN, Andy CLAESEN, Luc |
Issue Date: | 2010 | Publisher: | IEEE | Source: | 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip. p. 25-30. | Abstract: | This paper presents a novel binary fully adaptable window for incorporating in a stereo matching System-on-Chip (SoC) architecture. This architecture is fully scalable and parameterizable to allow for custom SoC implementations, as well as rapid prototyping on FPGAs. For each window a binary mask window is generated which selects the supporting pixels in the cost aggregation phase of the SAD algorithm. This selection is performed using color similarity and spatial distance metrics. Hardware resource utilization for a fixed window and an adaptable window cost aggregation is compared based on FPGA logic element use. | Notes: | Reprint Address: Motten, A (reprint author), Hasselt Univ tUL IBBT, Expertise Ctr Digital Media, Wetenschapspk 2, B-3590 Diepenbeek, Belgium Addresses: Hasselt Univ tUL IBBT, Expertise Ctr Digital Media, B-3590 Diepenbeek, Belgium E-mail Address: andy.motten@uhasselt.be, luc.claesen@uhasselt.be | Keywords: | component; stereo matching; adaptable window; cost aggregation; computer vision; System-on-Chip; FPGA | Document URI: | http://hdl.handle.net/1942/11273 | ISBN: | 978-1-4244-6470-8 | DOI: | 10.1109/VLSISOC.2010.5642626 | ISI #: | 000295220400005 | Category: | C1 | Type: | Proceedings Paper | Validations: | ecoom 2012 |
Appears in Collections: | Research publications |
Files in This Item:
File | Description | Size | Format | |
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A Binary Adaptable Window.pdf | Published version | 450.41 kB | Adobe PDF | View/Open |
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