Stress in Next Generation Interconnects

Abstract

Stress is becoming an increasingly critical parameter for all steps in back-end-of-line integration. As the k-value of dielectric spacers decreases their mechanical integrity scales accordingly, making the interconnect stack increasingly sensitive to barrier and copper stresses. These stresses need to be studied not only for as-deposited layers, but also during thermal processing. Stress relaxation of the barrier can for instance occur at elevated temperatures and result in severe dielectric deformation. Copper typically relaxes at elevated temperatures during thermal cycling and then builds-up thermal stress when cooled back to room temperature. However, the initial stress state can have a strong effect on the final microstructure. An example is shown here where a new growth mode, named `super-secondary-grain-growth, is stress induced and leads to grains of many tens of microns