Please use this identifier to cite or link to this item:
http://hdl.handle.net/1942/22825
Title: | SoC and FPGA Oriented High-quality Stereo Vision System | Authors: | LI, Yanzhe Huang, Kai CLAESEN, Luc |
Issue Date: | 2016 | Publisher: | IEEE Xplore | Source: | 2016 26th International Conference on Field Programmable Logic and Applications (FPL 2016), IEEE,p. 439-442 | Series/Report: | 2016 26th International Conference on Field Programmable Logic and Applications (FPL 2016) | Abstract: | Stereo matching is a crucial step for acquiring depth information from stereo images. However, it is still challenging to achieve good performance in both speed and accuracy for various stereo vision applications. In this paper, a hardware-compatible stereo matching algorithm is proposed; its associated hardware implementation is also presented. The proposed algorithm can produce high-quality disparity maps with the use of mini-census transform, segmentation-based adaptive support weight and effective refinement. Moreover, the proposed implementation is optimized as a fully pipelined and scalable hardware system. The proposed design is evaluated based on the Middlebury benchmarks and the average overall error rate is 6.10%. The experimental results indicate that the accuracy is competitive with some state-of-art software implementations. | Notes: | [Li, Yanzhe; Huang, Kai] Zhejiang Univ, Inst VLSI Design, Hangzhou, Zhejiang, Peoples R China. [Claesen, Luc] Hasselt Univ, Engn Technol Elect ICT Dept, B-3590 Diepenbeek, Belgium. | Keywords: | system-on-Chip; SoC; FPGA; depth vision; multi-camera | Document URI: | http://hdl.handle.net/1942/22825 | ISBN: | 9781509008513 | DOI: | 10.1109/FPL.2016.7577366 | ISI #: | 000386610400068 | Rights: | (C) IEEE | Category: | C1 | Type: | Proceedings Paper | Validations: | ecoom 2017 |
Appears in Collections: | Research publications |
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SOC and FPGA.pdf Restricted Access | Published version | 1.65 MB | Adobe PDF | View/Open Request a copy |
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