Please use this identifier to cite or link to this item: http://hdl.handle.net/1942/27667
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dc.contributor.authorGutierrez, Marina-
dc.contributor.authorLLORET, Fernando-
dc.contributor.authorPham, Toan T.-
dc.contributor.authorCanas, Jesus-
dc.contributor.authorReyes, Daniel F.-
dc.contributor.authorEon, David-
dc.contributor.authorPernot, Julien-
dc.contributor.authorAraujo, Daniel-
dc.date.accessioned2019-01-30T08:44:02Z-
dc.date.available2019-01-30T08:44:02Z-
dc.date.issued2018-
dc.identifier.citationNANOMATERIALS, 8(8) (Art N° 584)-
dc.identifier.issn2079-4991-
dc.identifier.urihttp://hdl.handle.net/1942/27667-
dc.description.abstractIn contrast to Si technology, amorphous alumina cannot act as a barrier for a carrier at diamond MOSFET gates due to their comparable bandgap. Indeed, gate leaks are generally observed in diamond/alumina gates. A control of the alumina crystallinity and its lattice matching to diamond is here demonstrated to avoid such leaks. Transmission electron microscopy analysis shows that high temperature atomic layer deposition, followed by annealing, generates monocrystalline reconstruction of the gate layer with an optimum lattice orientation with respect to the underneath diamond lattice. Despite the generation of gamma-alumina, such lattice control is shown to prohibit the carrier transfer at interfaces and across the oxide.-
dc.description.sponsorshipThis work was made possible through grants from the Spanish Ministry of Economy and Competitiveness (Hi-Volt, ref: TEC2014-54357-C2-2-R; and DiamMOS, ref: TEC2017-86347-C2-1-R projects) and from the European H2020 Program (Green Diamond, ref: SEP-210184415, project).-
dc.language.isoen-
dc.publisherMDPI-
dc.rightsCopyright 2018 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution-
dc.subject.otherdiamond; MOSFET; TEM; bandgap; dielectric functions; alumina; MPCVD-
dc.subject.otherdiamond; MOSFET; TEM; bandgap; dielectric functions; alumina; MPCVD-
dc.titleControl of the Alumina Microstructure to Reduce Gate Leaks in Diamond MOSFETs-
dc.typeJournal Contribution-
dc.identifier.issue8-
dc.identifier.volume8-
local.format.pages8-
local.bibliographicCitation.jcatA1-
dc.description.notes[Gutierrez, Marina; Lloret, Fernando; Canas, Jesus; Reyes, Daniel F.; Araujo, Daniel] Univ Cadiz, Fac Sci, Puerto Real 11510, Spain. [Lloret, Fernando] Univ Hasselt, Inst Mat Res, B-3590 Diepenbeek, Belgium. [Pham, Toan T.; Eon, David; Pernot, Julien] Univ Grenoble Alpes, UFR PHys, Ingn, Terre,Environm,Mecan, F-38042 Grenoble, France. [Pham, Toan T.; Eon, David; Pernot, Julien] CNRS, Inst NEEL, F-38042 Grenoble, France.-
local.publisher.placeBASEL-
local.type.refereedRefereed-
local.type.specifiedArticle-
local.bibliographicCitation.artnr584-
dc.identifier.doi10.3390/nano8080584-
dc.identifier.isi000443257500023-
item.contributorGutierrez, Marina-
item.contributorLLORET, Fernando-
item.contributorPham, Toan T.-
item.contributorCanas, Jesus-
item.contributorReyes, Daniel F.-
item.contributorEon, David-
item.contributorPernot, Julien-
item.contributorAraujo, Daniel-
item.accessRightsOpen Access-
item.fulltextWith Fulltext-
item.fullcitationGutierrez, Marina; LLORET, Fernando; Pham, Toan T.; Canas, Jesus; Reyes, Daniel F.; Eon, David; Pernot, Julien & Araujo, Daniel (2018) Control of the Alumina Microstructure to Reduce Gate Leaks in Diamond MOSFETs. In: NANOMATERIALS, 8(8) (Art N° 584).-
item.validationecoom 2019-
crisitem.journal.eissn2079-4991-
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