Please use this identifier to cite or link to this item: http://hdl.handle.net/1942/28386
Title: Two-topology based high-level simulation platform for NoC performance evaluation
Other Titles: 支持双拓扑结构的片上网络评估高层仿真平台
Authors: HU, Jing-jin
Pan, Yun
YAN, Xiao-Lang
MOTTEN, Andy 
CLAESEN, Luc 
Issue Date: 2013
Source: Application Research of Computers - 计算机应用研究, 30(9), p. 2827-2830
Abstract: Aiming at realizing efficient performance evaluation of NoC, and reducing SoC (system-on-chip) development period, this paper proposes a new high-level, high-efficiency, cycle accurate NoC simulation platform. Different from conventional tools, it supports evaluation for both 2D mesh and ring topologies and virtual channel extension in router structure design. It efficiently gives performance results, including average latency, throughput and energy consumption. Experimental results demonstrate that this simulation platform can simulate NoC behavior and obtain performance evaluation results, which provides high-efficiency verification method for NoC design and optimization.
Keywords: network-on-chip (NoC); performance evaluation; high-level simulation; ring topology; 2D mesh
Document URI: http://hdl.handle.net/1942/28386
Link to publication/dataset: http://www.arocmag.com/getarticle/?aid=b4956fbe187359a6
ISSN: 1001-3695
DOI: 10.3969/j.issn.1001-3695.2013.09.068
Category: A2
Type: Journal Contribution
Appears in Collections:Research publications

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