Please use this identifier to cite or link to this item: http://hdl.handle.net/1942/28734
Full metadata record
DC FieldValueLanguage
dc.contributor.authorVANDENABEELE, Thomas-
dc.contributor.authorUytterhoeven, Roel-
dc.contributor.authorDehaene, Wim-
dc.contributor.authorMENTENS, Nele-
dc.date.accessioned2019-07-16T11:29:23Z-
dc.date.available2019-07-16T11:29:23Z-
dc.date.issued2018-
dc.identifier.citation2018 28TH INTERNATIONAL SYMPOSIUM ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION (PATMOS), IEEE,p. 248-253-
dc.identifier.isbn9781538663653-
dc.identifier.issn2474-5456-
dc.identifier.urihttp://hdl.handle.net/1942/28734-
dc.description.abstractThis paper elaborates on the results of a thorough comparison between different AES S-box circuits in 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) technology of ST-Microelectronics. The three evaluated S-boxes are strategically chosen to provide a maximum coverage of the design space. Simulation results regarding area, speed, power and energy are presented and analyzed. Further, ultra low-power implementations are considered by simulating the circuits in the sub-threshold region. The presented performance comparison allows cryptographic hardware designers to select the most suitable S-box design for their resource-limited AES implementation.-
dc.description.sponsorshipSTMicroelectronics-
dc.language.isoen-
dc.publisherIEEE-
dc.relation.ispartofseriesInternational Symposium on Power and Timing Modeling Optimization and Simulation-
dc.rights2018 IEEE-
dc.subject.othersystematic performance comparison; cryptographic hardware designers; resource-limited AES implementation; FD-SOI technology; ultra low-power AES S-box circuit design ; fully depleted silicon-on-insulator technology; STMicroelectronics technology; size 28.0 nm; Si-
dc.titleA Systematic Performance Comparison of Ultra Low-Power AES S-Boxes-
dc.typeProceedings Paper-
local.bibliographicCitation.conferencedateJUL 02-04, 2018-
local.bibliographicCitation.conferencename28th IEEE International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)-
local.bibliographicCitation.conferenceplacePlatja Aro, SPAIN-
dc.identifier.epage253-
dc.identifier.spage248-
local.format.pages6-
local.bibliographicCitation.jcatC1-
dc.description.notes[Vandenabeele, Thomas; Mentens, Nele] Katholieke Univ Leuven, ES&S, Wetenschapspk 21, B-3590 Diepenbeek, Belgium. [Vandenabeele, Thomas; Mentens, Nele] Katholieke Univ Leuven, IMEC, ESAT, COSIC, Wetenschapspk 21, B-3590 Diepenbeek, Belgium. [Uytterhoeven, Roel; Dehaene, Wim] Katholieke Univ Leuven, MICAS, ESAT, Kasteelpk Arenberg 10, B-3001 Leuven Heverlee, Belgium.-
local.publisher.placeNEW YORK-
local.type.refereedRefereed-
local.type.specifiedProceedings Paper-
local.classIncludeIn-ExcludeFrom-List/ExcludeFromFRIS-
dc.identifier.doi10.1109/PATMOS.2018.8464160-
dc.identifier.isi000454761900039-
local.bibliographicCitation.btitle2018 28TH INTERNATIONAL SYMPOSIUM ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION (PATMOS)-
item.fulltextWith Fulltext-
item.contributorVANDENABEELE, Thomas-
item.contributorUytterhoeven, Roel-
item.contributorDehaene, Wim-
item.contributorMENTENS, Nele-
item.fullcitationVANDENABEELE, Thomas; Uytterhoeven, Roel; Dehaene, Wim & MENTENS, Nele (2018) A Systematic Performance Comparison of Ultra Low-Power AES S-Boxes. In: 2018 28TH INTERNATIONAL SYMPOSIUM ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION (PATMOS), IEEE,p. 248-253.-
item.accessRightsRestricted Access-
Appears in Collections:Research publications
Files in This Item:
File Description SizeFormat 
vandenabeele2018.pdf
  Restricted Access		Published version352.3 kBAdobe PDFView/Open    Request a copy
Show simple item record

Google ScholarTM

Check

Altmetric


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.