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http://hdl.handle.net/1942/28734
Title: | A Systematic Performance Comparison of Ultra Low-Power AES S-Boxes | Authors: | VANDENABEELE, Thomas Uytterhoeven, Roel Dehaene, Wim MENTENS, Nele |
Issue Date: | 2018 | Publisher: | IEEE | Source: | 2018 28TH INTERNATIONAL SYMPOSIUM ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION (PATMOS), IEEE,p. 248-253 | Series/Report: | International Symposium on Power and Timing Modeling Optimization and Simulation | Abstract: | This paper elaborates on the results of a thorough comparison between different AES S-box circuits in 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) technology of ST-Microelectronics. The three evaluated S-boxes are strategically chosen to provide a maximum coverage of the design space. Simulation results regarding area, speed, power and energy are presented and analyzed. Further, ultra low-power implementations are considered by simulating the circuits in the sub-threshold region. The presented performance comparison allows cryptographic hardware designers to select the most suitable S-box design for their resource-limited AES implementation. | Notes: | [Vandenabeele, Thomas; Mentens, Nele] Katholieke Univ Leuven, ES&S, Wetenschapspk 21, B-3590 Diepenbeek, Belgium. [Vandenabeele, Thomas; Mentens, Nele] Katholieke Univ Leuven, IMEC, ESAT, COSIC, Wetenschapspk 21, B-3590 Diepenbeek, Belgium. [Uytterhoeven, Roel; Dehaene, Wim] Katholieke Univ Leuven, MICAS, ESAT, Kasteelpk Arenberg 10, B-3001 Leuven Heverlee, Belgium. | Keywords: | systematic performance comparison; cryptographic hardware designers; resource-limited AES implementation; FD-SOI technology; ultra low-power AES S-box circuit design ; fully depleted silicon-on-insulator technology; STMicroelectronics technology; size 28.0 nm; Si | Document URI: | http://hdl.handle.net/1942/28734 | ISBN: | 9781538663653 | DOI: | 10.1109/PATMOS.2018.8464160 | ISI #: | 000454761900039 | Rights: | 2018 IEEE | Category: | C1 | Type: | Proceedings Paper |
Appears in Collections: | Research publications |
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