Please use this identifier to cite or link to this item: http://hdl.handle.net/1942/31553
Title: Heterogeneous Integration and Fabrication of III-V MOS Devices in a 200mm Processing Environment
Authors: Waldron, Niamh
Ngoc Duy Nguyen
Lin, Dennis
BRAMMERTZ, Guy 
Vincent, Benjamin
Firrincieli, Andrea
Winderick, Gillis
Sioncke, Sonja
de Jaeger, Brice
Wang, Gang
Mitard, Jerome
Wang, Wei-E
Heyns, Marc
Caymax, Matty
MEURIS, Marc 
Absil, Philippe
Hoffman, Thomas Y.
Issue Date: 2011
Publisher: ELECTROCHEMICAL SOC INC
Source: DIELECTRICS IN NANOSYSTEMS -AND- GRAPHENE, GE/III-V, NANOWIRES AND EMERGING MATERIALS FOR POST-CMOS APPLICATIONS 3, ELECTROCHEMICAL SOC INC, p. 299 -309
Abstract: We report on the fabrication of MOS capacitors on 200 mm virtual GaAs substrates using a Si CMOS processing environment. The fabricated capacitors were comparable to those processed on bulk GaAs material. Topside contact was made to the GaAs using a novel CMOS compatible self-aligned NiGe contact scheme resulting in a measured contact resistance of 0.26 Omega.cm. Cross-contamination from various III-V substrates was investigated and it was found that by limiting the thermal budget to <= 300 degrees C cross-contamination from the outgassing of In, Ga and As could be eliminated. For wet processing the judicious choice of recipe and processing conditions resulted in no significant cross-contamination being detected as determined by TXRF monitoring. This achievement enables III-V device production using state-of-the-art Si processing equipment.
Notes: Waldron, N (corresponding author), IMEC, Kapeldreef 75, B-3001 Louvain, Belgium.
Keywords: EPITAXIAL-GROWTH;GE;GAAS;SI
Document URI: http://hdl.handle.net/1942/31553
ISBN: 978-1-60768-214-1
978-1-56677-864-0
DOI: 10.1149/1.3569922
ISI #: WOS:000309539300027
Category: C1
Type: Proceedings Paper
Appears in Collections:Research publications

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