Please use this identifier to cite or link to this item: http://hdl.handle.net/1942/31559
Title: Challenges for introducing Ge and III/V devices into CMOS technologies
Authors: Heyns, M.
Alian, A.
BRAMMERTZ, Guy 
Caymax, M.
Eneman, G.
Franco, J.
Gencarelli, F.
Groeseneken, G.
Hellings, G.
Hikavyy, A.
Houssa, M.
Kaczer, B.
LIN, Dan 
Loo, R.
Merckling, C.
MEURIS, Marc 
Mitard, J.
Nyns, L.
Sioncke, S.
Vandervorst, W.
Vincent, B.
Waldron, N.
Witters, L.
Issue Date: 2012
Publisher: IEEE
Source: 2012 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), IEEE,
Abstract: High mobility channel materials and new device structures will be needed to meet the power and performance specifications in future technology nodes. In these new material systems and devices various electrically active defects are present at or close to the interface between the high-k dielectric and the alternative channel material which are a major concern for both the performance and the reliability of these new devices.
Notes: Heyns, M (corresponding author), IMEC, Kapeldreef 75, B-3001 Louvain, Belgium.
Keywords: CMOS;Germanium;III/V;defects;ATOMIC LAYER DEPOSITION;SURFACE SEGREGATION;PASSIVATION;GROWTH;PERFORMANCE;NBTI
Document URI: http://hdl.handle.net/1942/31559
ISBN: 978-1-4577-1679-9
ISI #: WOS:000309183100082
Category: C1
Type: Proceedings Paper
Appears in Collections:Research publications

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