High Quality Ge Virtual Substrates on Si Wafers with Standard STI Patterning

Abstract

Further improving complementary metal oxide semiconductor performance beyond the 22 nm generation likely requires the use of high mobility channel materials, such as Ge for p-type metal oxide semiconductor (pMOS) and III/V for n-type metal oxide semiconductor devices. The complementary integration of both materials on Si substrates can be realized with selective epitaxial growth. We present two fabrication schemes for Ge virtual substrates using Si wafers with standard shallow trench isolation (STI). This reduces the fabrication cost of these virtual substrates as the complicated isolation scheme in blanket Ge can be omitted. The low topography enables integration of ultrathin high-k gate dielectrics. The fabrication schemes are also compatible with uniaxial stress techniques. Both modules include an annealing step at 850 degrees C to reduce the threading dislocation densities down to 4 x 10(8) and 1 x 10(7) cm(-2), respectively. We are able to fabricate high quality Ge virtual substrates for pMOS devices as well as suitable starting surfaces for selective epitaxial III/V growth. The latter are illustrated by preliminary results of selective epitaxial InGaAs growth on virtual Ge substrates. (C) 2009 The Electrochemical Society. [DOI: 10.1149/1.3244564] All rights reserved.