Ge and III/V devices for advanced CMOS

Please use this identifier to cite or link to this item: http://hdl.handle.net/1942/31639

Title:	Ge and III/V devices for advanced CMOS
Authors:	Heyns, Marc Adelmann, Christoph BRAMMERTZ, Guy Brunco, David Caymax, Matty De Jaeger, Brice Delabie, Annelies Eneman, Geert Houssa, Michel Lin, Dennis Martens, Koen Merckling, Clement MEURIS, Marc Mittard, Jerome Penaud, Julien Pourtois, Geoffrey Scarrozza, Marco Simoen, Eddy Sioncke, Sonja Wang, Wei-E
Issue Date:	2009
Publisher:	IEEE
Source:	ULIS 2009: 10TH INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION OF SILICON, IEEE, p. 83 -86
Abstract:	The use of Ge and III/V materials for future CMOS applications is investigated. Good passivation of the Ge surface can be obtained by either GeO2 or Si passivation. Short channel Ge pMOS devices with low EOT are fabricated using Si passivation at 350 and 500 degrees C. The passivation of III/V materials is a very challenging topic. Some critical issues and passivation schemes are discussed.
Notes:	Heyns, M (corresponding author), IMEC, Kapeldreef 75, B-3001 Louvain, Belgium. marc.heyns@imec.be
Document URI:	http://hdl.handle.net/1942/31639
ISBN:	978-1-4244-3705-4
DOI:	10.1109/ULIS.2009.4897544
ISI #:	WOS:000266761300020
Category:	C1
Type:	Proceedings Paper
Appears in Collections:	Research publications

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