Epitaxial Ge on Standard STI Patterned Si Wafers: High Quality Virtual Substrates for Ge pMOS and III/V nMOS

Abstract

Further improving CMOS performance beyond the 22 nm generation likely requires the use of high mobility channel materials, like Ge for pMOS and III/V for nMOS devices. The complementary integration of both materials on Si substrates can be realized with selective epitaxial growth. We present two fabrication schemes for Ge virtual substrates using Si wafers with standard Shallow Trench Isolation. This reduces the fabrication cost of these virtual substrates as the complicated isolation scheme in blanket Ge can be omitted. The low topography enables integration of ultra thin high-K gate dielectrics. The fabrication schemes are also compatible with uni-axial stress techniques. Both modules include an annealing step at 850 degrees C to reduce the threading dislocation density down to 4x10(8) cm(-2) and 1x10(7) cm(-2), respectively. We are able to fabricate high quality Ge virtual substrates for pMOS devices as well as suitable starting surfaces for selective epitaxial III/V growth. The latter one will be illustrated by preliminary results of selective epitaxial InGaAs growth on virtual Ge substrates.