High-kappa Dielectrics and Interface Passivation for Ge and III/V Devices on Silicon for advanced CMOS

Please use this identifier to cite or link to this item: http://hdl.handle.net/1942/31655

Title:	High-kappa Dielectrics and Interface Passivation for Ge and III/V Devices on Silicon for advanced CMOS
Authors:	Heyns, Marc Bellenger, Florence BRAMMERTZ, Guy Caymax, Matty De Jaeger, Brice Delabie, Annelies Eneman, Geert Houssa, Michel Lin, Dennis Martens, Koen Merckling, Clement MEURIS, Marc Mitard, Jerome Penaud, Julien Pourtois, Geoffrey Scarrozza, Marco Simoen, Eddy Sioncke, Sonja Van Elshocht, Sven Wang, Wei-E
Issue Date:	2009
Publisher:	ELECTROCHEMICAL SOC INC
Source:	PHYSICS AND TECHNOLOGY OF HIGH-K GATE DIELECTRICS 7, ELECTROCHEMICAL SOC INC, p. 51 -65
Series/Report:	ECS Transactions
Abstract:	The use of Ge and III/V materials for future CMOS applications is investigated. Passivation of the Ge surface can be obtained by either GeO2 or a thin Si layer. Short channel Ge pMOS devices with low EOT are fabricated. The passivation of III/V materials is a very challenging topic. Some critical issues and passivation schemes are investigated and the performance of inversion channel MOSFET's on In0.53Ga0.47As with ALD Al2O3 is discussed.
Keywords:	MOLECULAR-BEAM EPITAXY;GATE;SEMICONDUCTORS;SEGREGATION;MOSFET
Document URI:	http://hdl.handle.net/1942/31655
ISBN:	978-1-60768-093-2 978-1-56677-743-8
DOI:	10.1149/1.3206606
ISI #:	WOS:000338086300005
Category:	C1
Type:	Proceedings Paper
Appears in Collections:	Research publications

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