Study of the behaviour of oxide related degradation mechanisms of smart power based transistors

Abstract

In this work we presented the analysis of the HCI behaviour of a high voltage nDMOS transistor. We describe the effects of hot hole/electron injection in the channel region and/or the gate controlled drift region of DMOS transistors. A first mechanism is attributed to decreased electron mobility due to increased carrier scattering upon Dit formation in the channel or beyond whereas a second mechanism occurs in the gate overlapped drift region of the device and is due to hot-hole injection and trapping. The competition of both mechanisms depends strongly on the stress conditions. In addition to these different degradation mechanisms, under high stress conditions source side injection takes place, which leads to rather moderate changes of the linear drain current (Id,lin) but significant changes of the saturation drain current (Id,sat) and the threshold voltage (Vt). The mechanisms could be identified by analysis of the electrical data and by performing Charge Pumping (CP) experiments. The experimental results give clear evidence for the existence of a source-side injection degradation component. Higher nLDD dose clearly reduces this effect. The best suitable model has been discussed and adapted to this new technology and detailed TCAD simulations were also performed, supporting the proposed model.