Real-Time Stereo Vision Hardware Architecture Suitable for Multiple Platforms

Abstract

This paper presents a real-time stereo vision Systemon- Chip (SoC) architecture for a depth-field generation processor as required in 3D TV applications. This architecture is fully scalable and parameterizable to allow for custom SoC implementations, as well as rapid prototyping on FPGAs. An onchip memory block architecture is used that allows parallel access to all pixels located in a chosen window of the image. A real-time stereo matching calculation at a frame rate of 56 Hz with a resolution of 800x600, a disparity of 80 and a window size of 11x11 has been realized using this architecture without the need for external memories.