Please use this identifier to cite or link to this item: http://hdl.handle.net/1942/14263
Title: Adaptive Memory Architecture for Real-Time Image Warping
Authors: MOTTEN, Andy 
CLAESEN, Luc 
Pan, Yun
Issue Date: 2012
Publisher: IEEE
Source: Tahar, Sofiene; Byrd, Greg; Schneider, Klaus; Pradip, Bose (Ed.). 2012 IEEE 30th International Conference on Computer Design (ICCD), p. 466-471
Abstract: This paper presents a real time image warping module implemented in hardware. A look-up table (LUT) based reverse mapping is used to relate the source image to the warped image. Frame buffers or line buffers are often used to temporally store the source image. However these methods do not take the underlying pattern of the reverse mapping coordinates into account. The presented architecture uses an adaptable memory allocation which can change the depth and the position of the line buffer between lines. A real-time stereo rectification use case has been implemented to validate the operation of this module. Depending on the scenario, the memory consumption can be reduced by a factor of two and more. A real-time image warping module for video cameras has been implemented in a single FPGA, without the use of off-chip memories.
Notes: Reprint Address: Motten, A (reprint author), Hasselt Univ, tUL, IBBT, Expertise Ctr Digital Media, Diepenbeek, Belgium. Addresses: Hasselt Univ, tUL, IBBT, Expertise Ctr Digital Media, Diepenbeek, Belgium
Keywords: warping; real-time; rectification; memory architecture; system-on-chip; FPGA
Document URI: http://hdl.handle.net/1942/14263
ISBN: 978-1-4673-3050-3
DOI: 10.1109/ICCD.2012.6378680
ISI #: 000316948500074
Category: C1
Type: Proceedings Paper
Validations: ecoom 2014
Appears in Collections:Research publications

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