Please use this identifier to cite or link to this item: http://hdl.handle.net/1942/7782
Title: Electrical performance, reliability and microstructure of sub-45 nm copper damascene lines fabricated with TEOS backfill
Authors: Leaming-Sphabmixay, K.
VAN OLMEN, Jan 
Moon, K. J.
VANSTREELS, Kris 
D'HAEN, Jan 
Tokei, Z.
List, S.
Beyer, G.
Issue Date: 2007
Publisher: ELSEVIER SCIENCE BV
Source: MICROELECTRONIC ENGINEERING, 84(11). p. 2681-2685
Abstract: The fabrication of narrow Cu trenches using a conformal TEOS backfill approach is shown. Cu trenches with widths down to 3040 nm were achieved. With an adequate Ta-based PVD barrier and Cu seed layer scheme, narrow Cu lines with high yield were obtained. An increase of the electrical resistivity in the narrowest dimensions was observed as a result of the size effect. Electromigration assessment demonstrated that a bilayer TaN/Ta barrier outperforms the monolayer Ta barrier. Electron backscattering diffraction (EBSD) analysis was carried out to determine grain orientation and texture in narrow copper trenches. For the first time, EBSD data reveal that Cu trenches down to 30-40 run wide have mostly a random texture. The narrower the Cu lines get, the weaker the (I 11) texture with both monolayer and bilayer Ta-based barriers. (c) 2001 Published by Elsevier B.V.
Notes: IMEC, Louvain, B-3001 Belgium. Hasselt Univ, Inst Mat Res, Diepenbeek, B-3590 Belgium. Div IMOMEC, Diepenbeek, B-3590 Belgium.Van Olmen, J, IMEC, Kapeldreef 75, Louvain, B-3001 Belgium.
Keywords: metallization and barrier materials, interconnects, process integration, effect of scaling
Document URI: http://hdl.handle.net/1942/7782
ISSN: 0167-9317
e-ISSN: 1873-5568
DOI: 10.1016/j.mee.2007.06.009
ISI #: 000250657200045
Category: A1
Type: Journal Contribution
Validations: ecoom 2008
Appears in Collections:Research publications

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